1. Field of the Invention
This invention relates to a communication apparatus having fault tolerance for use in, for example, a multiplex transmission system for digital communication among balanced type communication apparatuses, each of which employs at least two transmission lines.
2. Description of the Related Art
Various devices to improve reliability in communication have been made for conventional data communication systems. An example of such devices is to let a communication apparatus have fault tolerance, which is the capability of a communication apparatus to externally correctly perform all or part of the predetermined functions without coming to a dead stop even if the performance of the apparatus decreases due to an occurrence of a fault or failure.
In a conventional fault-tolerant balanced type communication apparatus employing two transmission lines (or buses), when the electric potential of one of the transmission lines is fixed at a given value (including zero) due to some cause (namely, the failure of one of the transmission lines), the other of the transmission lines, which can keep sending communication signals normally, is effectively used. This is realized by inserting a capacitor in each of the transmission lines and separating a capacitor and a corresponding transmission line in a d.c. manner. At that time, the d.c. component of the voltage level of a communication signal having passed through a capacitor is removed therefrom, so that the voltage level thereof fluctuates in the vicinity of zero potential and thus may be negative. It is, therefore, necessary to provide a circuit for adding the removed d.c. component to the voltage level of the communication signal after the communication signal passed through the capacitor.
FIG. 1 shows the circuit configuration of the conventional balanced-type communication apparatus. If, for instance, a positive polarity bus 52 fails, the input voltage to the noninverting input terminal (hereunder referred to as the positive polarity input terminal) of a comparator IC501 connected to the positive polarity bus 52 is equal to a d.c. component to be added by a d.c. component addition circuit 54. On the other hand, a d.c. component is added by a d.c. component addition circuit 53 to a communication signal passing through a negative polarity bus 51, which does not fail, by way of a capacitor C501. Thereafter, the communication signal is input to the inverting input terminal (hereunder referred to as the negative polarity input terminal) of the comparator IC501. Further, a modulation of the input communication signal is performed in the comparator IC501 by employing the d.c. component input to the positive polarity input terminal (namely, the noninverting input terminal) thereof as a threshold value. Incidentally, in the d.c. component addition circuit 53, a source voltage Vcc is divided by resistors R501 and R502. Further, a voltage obtained as the result of the division is applied to the negative polarity bus 51 through a resistor 503. Similarly, in the d.c. component addition circuit 54, the source voltage Vcc is divided by resistors R504 and R505. Further, a voltage obtained as the result of the division is applied to the positive polarity bus 52 through a resistor 506.
However, in this conventional system, the d.c. component added to the communication signal passing through the negative polarity bus 51 is not uniquely determined in accordance with the value determined by the d.c. component addition circuit 53. Namely, the d.c. component varies with the duty factor or ratio of the communication signal and with the time having passed since the initiation of an inputting of pulses. This due to the fact that the d.c. component added by the d.c. component addition circuit 53 does not become constant until the capacitor C501 is charged according to a time constant determined by the resistors R501 and R503 and the capacitor 501.
Thus the d.c. component of the communication signal having passed through the capacitor C501 gradually changes until a transient time t passes since the initiation of an inputting of the communication signal to as indicated by a dashed curve in FIG. 2. This results in instability of the threshold value employed in the comparator IC501. Therefore, where the positive polarity bus 52 or the negative polarity bus 51 has a capacitive component, the waveform of the communication signal is deformed. Consequently, the conventional system has a drawback in that there occurs a difference or error between the values of the duty factor respectively measured before and after the demodulation of the communication signal.
As a technical countermeasure for eliminating such a drawback, an improved conventional system, the configuration of which is disclosed in Japanese Unexamined Patent Publication (Kokai Tokkyo Koho) Official Gazette No. 1-261047, has been developed. Namely, as is shown in FIG. 3, a negative polarity bus 71 connecting a comparator IC701 to a capacitor C701 is connected by a non-linear element such as a diode D701 with a positive polarity bus 72 connecting a comparator IC702 to a capacitor C702 in this system. Further, the source voltage Vcc is applied to the anode of the diode D701 through a resistor R702. On the other hand, the cathode of the diode D701 is grounded through a resistor R701. This circuit utilizes the property of a diode that a voltage developed across a diode is nearly constant independent of a current flowing through the diode.
However, the forward voltage of the diode D701 used to connect the negative polarity bus 71 to the positive polarity bus 72 of the conventional system has a temperature characteristic. If, for example, the positive polarity bus 72 fails in a situation where temperature of a working environment varies, the forward voltage Vf of the diode D701 changes and thus the d.c. components of the voltages Vin.sup.+ and Vin.sup.- applied to the comparator IC701 vary as illustrated in FIG. 4. Incidentally, the voltages Vin.sup.+ and Vin.sup.- of FIG. 4 are input to the noninverting and inverting input terminals (namely, the positive and negative polarity input terminals) of the comparator IC701, respectively.
Thus the threshold value varies due to, especially, change in the input voltage Vin.sup.+ . Therefore, this improved conventional system has a defect in that in case where the communication signal is deformed due to distributed capacity of the buses, the pulse width of an output signal of the comparator IC701 changes between t.sub.1 and t.sub.2 (namely, t.sub.1 .noteq.t.sub.2) after the demodulation as illustrated in FIG. 4. The present invention is created to eliminate such a defect of the conventional system.
It is, accordingly, an object of the present invention to provide a fault tolerant receiver employing balanced type transmission lines, which can correctly perform a demodulation even when one of the transmission lines fails and temperature of a working environment varies.
Further, in a conventional fault-tolerant balanced type communication apparatus employing at least two transmission lines, when the electric potential of one of the transmission lines is fixed at a given value (including zero) due to some cause (namely, when one of the transmission lines fails), reception data can be maintained as long as the other transmission line operates normally, though the anti-noise performance thereof, which is a merit or advantage of the balanced type communication, is degraded.
It is, however, undesirable to leave the fault in communication apparatus. Thus it is necessary to detect which of the transmission lines fails and to perform some countermeasures (for instance, to inform a user of the detected transmission line failure).
FIG. 5 shows an example of a failure detection circuit for detecting which of the transmission lines fails, which is disclosed in German Laid-open Patent Application (Offenlegungsschrift) DE 3826774 A1.
In the circuit of FIG. 5, a counter 24 is periodically incremented and is reset in response to a demodulation signal sent from a comparator 20. A failure of a negative polarity signal line 41 or of a positive polarity signal line 42 is detected by this counter 24 and a central processing unit (hereunder abbreviated as CPU) 25.
Namely, in the circuit shown in FIG. 5, when the negative and positive polarity signal lines 41 and 42 are normal, a demodulation signal is output from the comparator 20. Thus the counter 24 is reset. In contrast, when one of the negative and positive polarity signal lines 41 and 42 fails, the comparator 20 does not output a demodulation signal. Hence, the counter 24 is kept incremented periodically.
Further, when the value of the counter 24 reaches a predetermined amount, the counter 24 outputs an error signal to the CPU 25. Then, the CPU 25 turns on an analog switch 21 by way of a status register 26. Thereupon, a signal having a prescribed voltage level of Vcc/2 (volts (V)) is supplied to the positive polarity signal line 42 through a voltage follower 23 and further is input to the noninverting input terminal (namely, the positive polarity input terminal) of the comparator 20. As the result, the counter 24 is reset when a demodulation is performed by the counter 24. Thereby, the CPU 25 can detect a failure of the positive polarity signal line 42.
However, in case where a demodulation is not effected by the comparator 24 yet, the counter 24 is kept incremented again. Thereafter, when the value of the counter 24 reaches the predetermined one, the counter 24 outputs an error signal to the CPU 25 again. Subsequently, the CPU 25 turns on an analog switch 22 by way of the status register 26. Then, a signal having the prescribed voltage level of Vcc/2 (V) is fed through the voltage follower 23 to the negative polarity signal line 41 and further is input to the inverting input terminal (namely, the negative polarity input terminal) of the comparator 20.
At that time, if a demodulation is performed by the comparator 20, the counter 24 is reset. Thereby, the CPU 25 can detect a failure of the negative polarity signal line 41.
However, in case of the conventional detection circuit, when a detection of a failure in the negative polarity signal line 41 and the positive polarity signal line 42 is effected, it is necessary to subsequently perform failure detection operations of the counter 24 and the CPU 25 twice. This is because a selection of the analog switches 21 and 22 are controlled by the CPU 25. Thus the conventional communication apparatus provided with this failure detection circuit has a drawback in that it takes time to determine which of the negative and positive polarity buses fails. The present invention is intended to eliminate this drawback of the conventional communication apparatus.
It is, therefore, another object of the present invention to provide a fault-tolerant communication apparatus employing balanced type transmission lines, which can perform a demodulation even if one of the transmission lines fails, and can reduce time required for detecting a failure in the transmission lines.